RIGHT
 








logo


PROGRAM Slides and Webcast (coming soon)


 

Session 1: Hardware Accelerators - Can they Deliver on the Promise of Application Performance?

Chair: Henri Calandra, Technical Advisor, Depth Imaging & HPC, Total

Experiences with Seismic Algorithms on GPUs

Scott Morton, Manager, Geophysical Technology, Hess Corporation

Abstract: At Hess we have long monitored GPUs and other accelerator technologies, testing the most promising approaches when we judge they may have a price-to-performance ratio better than PC clusters. In this talk, we will describe our experiences and results monitoring and testing GPUs to run various seismic processing algorithms.  Currently, we are seeing performance improvement of GPUs over CPUs which varies significantly with algorithm but is high enough so that we are building a substantial GPU-based cluster.

Optimal Thread-Level Parallelism on Cell and x86-based Multi-Core Architectures Using the Same Code: A Case Study Using Elastic Finite-Difference Modeling.

Samuel Brown, Utah Tomography & Modeling/Migration Consortium, University of Utah

Abstract: I present a control-compute threading framework and a set of abstractions which enable development of efficient multi-threaded numerical applications to target Cell and x86 architectures.  Computationally intensive kernels are confined to compute threads, while the control thread handles file I/O and thread synchronization.  The development process is simplified by adoption of a uniform synchronization strategy, and architecture-specific code is kept to a minimum and handled with compilation macros.  A 2D elastic finite-difference modeling code is developed and benchmarked to demonstrate the methodology.  Benchmarking results show superior scaling beyond two threads for the heterogeneous Cell processor over homogeneous Intel multi-core processors.

CGGVeritas accelerators experience,

Guillaume Thomas-Collignon, CGGVeritas

Abstract: We present CGGVeritas's experience on various accelerator technologies applied to seismic imaging, through the example of porting a wave equation migration. Three case studies are presented: FPGAs with Cray XD-1, IBM Cell with QS20 blade, and GPGPU with nVidia Cuda on G80. Both implementation and perfomance issues are discussed.

Session 2: Programming Models and Tools for Emerging Computer Architectures,
Chair: Jan E. Odegard, Executive Director, Ken Kennedy Institute for Information Technology, Rice University

Portable Parallel Programming for Multicore Computing,

Vivek Sarkar, E.D. Butcher Professor of Computer Science, Rice University

Abstract: The computer industry is at a major inflection point in its hardware roadmap due to the end of a decades-long trend of exponentially increasing clock frequencies.  It is widely agreed that spatial parallelism in the form of multiple power-efficient cores must be exploited to compensate for this lack of frequency scaling.  Unlike previous generations of hardware evolution, this shift towards multicore and manycore computing will have a profound impact on software.  In this talk, we will focus on the programming problem for homogeneous and heterogeneous multicore processors.  Homogeneous multicore processors are interesting targets for research because of their sheer ubiquity and the new challenges that they pose for software enablement relative to SMPs of the past.  Heterogeneous accelerators such as GPGPUs, Cell, and ClearSpeed are interesting because of their potential to deliver order-of-magnitude improvements in performance and power efficiency relative to homogeneous multicore processors, while posing even greater challenges for software enablement.

The Habanero project at Rice University was initiated in Fall 2007 to address the multicore software challenge by developing new programming technologies --- languages, compilers, managed runtimes, concurrency libraries, and tools --- that support portable parallel abstractions for future multicore hardware with high productivity and high performance.  Our goal is to ensure that future software rewrites are done on software platforms that enable application developers to reuse their investment across multiple generations of homogeneous and heterogeneous multicore hardware.  We also envision broader impact of this research including: updating the foundations of parallel software in introductory Computer Science courses, building an open source test-bed to grow the ecosystem of researchers in the parallel software area, and using our research infrastructure as the basis for building reference implementations of future industry standards.

Fine-tuning your HPC Investments with Performance Analysis,

John Mellor-Crummey, Associate Professor, Computer Science, Rice University

Abstract: The gap between typical and peak performance of computer systems is growing with each new generation of processors. To get the most out of your investment in high-performance computing systems, performance analysis and tuning have become increasingly important. This talk will describe work in Rice University's HPCToolkit project, which is building a new generation of open-source suite of multi-platform tools for profile-based performance analysis of sequential and parallel applications. The toolkit consists of components for collecting precise performance measurements of fully-optimized executables without adding instrumentation, analyzing application binaries to understand the structure of optimized code, and correlating measurements with program structure, as well as a user interface that supports top-down analysis of performance data.

Addressing Heterogeneity in Manycore Applications: RTM Simulation Use Case,

Stéphane Bihan,Technical Sales Engineer, CAPS Enterprise

Abstract
: Hardware accelerators can offer tremendous speedups for specific tasks, either integrated on-chip or available via a hypertransport or PCIexpress interconnect. Most of hardware vendors now provide tools that specifically address the programming of the stream cores. Portability, maintenance and hardware resource configuration is still an issue with fast changing hardware platforms.
In this talk, we present HMPP a new hybrid multicore parallel programming environment that, while preserving the legacy code, integrates the use of hardware accelerators, keeps the application independent from fast changing hardware platforms and offers various configuration interoperability. We will endup with a RTM Simulation Use Case.

Panel 1: Heterogeneous Multicore – The Answer to Your Dreams or Your Worst Nightmare?

  1. Stéphane Bihan, CAPS Enterprise
  2. Samuel Brown, University of Utah
  3. John Mellor-Crummey, Rice University
  4. Scott Morton, Hess Corporation
  5. Vivek Sarkar, Rice University
  6. Guillaume Thomas-Collignon, CGGVeritas

Panel 2: Storage and i/o Solutions in Support of Seismic Processing and Reservoir Modeling

Chair: Keith Gray, Manager of High Performance Computing, BP

    1.  Jeff Denworth, Director of Platform Solutions, DataDirect Networks
    2.  Per Brashers, Sr. Software Consultant, EMC NAS Engineering
    3.  Larry Jones, VP Marketing, Panasas
    4.  Sean Cochrane, Global Storage Architect, Sun Microsystems
    5.  Tom Reed, Professional Services Manager, SGI
    6.  Dan Lee, VP Technical Computing and Storage Practice, IDC


 

Hosted by: rice logo

 

| Program |Speakers | Sponsors | Contact | Home | Workshop Site

 

Workshop Organizers:
Keith Gray, BP; Henri Calandra, Total; Chap Wong, Chevron; Jan Odegard, Rice University; Ebb Pye